In order to realize highly integrated semiconductor devices, semiconductor patterns become finer. However, as the patterns become finer, a line pitch becomes smaller. The small line pitch causes an increase in capacity C between lines, thereby causing a large signal delay. A signal delay τ is represented by Eq. 1 below:τ=R×C  Eq. 1,where τ is a signal delay, R is a line resistance and C is a capacity between lines.
As can be seen from Eq. 1 above, it is important to decrease a capacity C between lines in order to decrease a signal delay τ.
In order to decrease a capacity C between lines without widening a line pitch, it is preferable to reduce a dielectric constant of an interlayer insulating film arranged between lines. A representative example of an interlayer insulating film is an SiO2 film. The SiO2 film has a dielectric constant of about 4. Accordingly, one solution to reduce a capacity C between lines is to use an insulating film having a dielectric constant less than 4, what may also be referred to as a low dielectric film (low-k film), as an interlayer insulating film.
Another solution is to remove an interlayer insulating film interposed between lines and form air gaps between the lines. This is because vacuum has a dielectric constant of 1 (see, e.g., Japanese Patent Laid-open Application Nos. 2000-208622 and 2007-74004).
By forming air gaps between lines, the dielectric constant between the lines approximates to 1.
However, in a semiconductor device including air gaps between the lines, which have a dielectric constant of about 1, a solid body such as an interlayer insulating film is not present between the lines. Accordingly, in such a semicondcutror device, how to control a line shape is an essential issue.
Further, the lines are exposed after formation of the air gaps. Accordingly, how to prevent deterioration (e.g., oxidation) of the exposed lines is another essential issue.